The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 05, 2011
Filed:
Jun. 06, 2008
Applicants:
Jung Lee, Sunnyvale, CA (US);
Mahesh Gopalan, Sunnyvale, CA (US);
Inventors:
Jung Lee, Sunnyvale, CA (US);
Mahesh Gopalan, Sunnyvale, CA (US);
Assignee:
Uniquify, Incorporated, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/04 (2006.01); G06F 1/12 (2006.01); G06F 12/00 (2006.01); H03K 19/173 (2006.01); H03K 19/00 (2006.01); G11C 7/00 (2006.01); G11C 8/00 (2006.01); G11C 29/00 (2006.01); G01R 35/00 (2006.01); G01R 31/00 (2006.01); G01R 31/28 (2006.01); G01B 5/02 (2006.01);
U.S. Cl.
CPC ...
Abstract
A DDR memory controller is described wherein a core domain capture clock is created by programmably delaying the core clock of the memory controller. The delay of this capture clock is calibrated during a power on the initialization sequence in concert with a DDR memory in a system environment, thereby minimizing the effects of system delays and increasing both device and system yield. An additional embodiment also includes programmably delaying the incoming dqs signal.