The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 05, 2011
Filed:
Jan. 11, 2008
Vijay Kumar Reddy, Plano, TX (US);
Andrew Marshall, Dallas, TX (US);
Siraj Akhtar, Richardson, TX (US);
Srikanth Krishnan, Richardson, TX (US);
Karan Singh Bhatia, Plano, TX (US);
Vijay Kumar Reddy, Plano, TX (US);
Andrew Marshall, Dallas, TX (US);
Siraj Akhtar, Richardson, TX (US);
Srikanth Krishnan, Richardson, TX (US);
Karan Singh Bhatia, Plano, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
One embodiment relates to an on-chip power amplifier (PA) test circuit. In one embodiment, a PA test circuit comprises a controllable oscillator (CO) configured to generate a radio frequency (RF) signal, a parallel resonant circuit tuned to the radio frequency, a pre-power amplifier (PPA) coupled to the CO and the parallel resonant circuit, the PPA configured to amplify and drive the RF signal from an output of the PPA into a load. The test circuit may further comprise a first transmission gate configured to couple the RF signal from the CO to an input of the PPA. One testing methodology for a PA test circuit comprises stressing the PPA with an RF signal, measuring a characteristic of the PPA, determining stress degradation from the characteristic measurements, and repeating the stressing and characteristic measurements until a maximum stress degradation is achieved or a maximum stress has been applied.