The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 05, 2011

Filed:

Jul. 06, 2009
Applicants:

Wei Tan, Bloomington, MN (US);

Nurul Amin, Woodbury, MN (US);

Insik Jim, Eagan, MN (US);

Ming Sun, Eden Prairie, MN (US);

Venu Vaithyanathan, Bloomington, MN (US);

Youngpil Kim, Eden Prairie, MN (US);

Chulmin Jung, Eden Prairie, MN (US);

Inventors:

Wei Tan, Bloomington, MN (US);

Nurul Amin, Woodbury, MN (US);

Insik Jim, Eagan, MN (US);

Ming Sun, Eden Prairie, MN (US);

Venu Vaithyanathan, Bloomington, MN (US);

YoungPil Kim, Eden Prairie, MN (US);

Chulmin Jung, Eden Prairie, MN (US);

Assignee:

Seagate Technology LLC, Scotts Valley, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A non-volatile memory cell with a programmable unipolar switching element, and a method of programming the memory element are disclosed. In some embodiments, the memory cell comprises a programmable bipolar resistive sense memory element connected in series with a programmable unipolar resistive sense switching element. The memory element is programmed to a selected resistance state by application of a selected write current in a selected direction through the cell, wherein a first resistance level is programmed by passage of a write current in a first direction and wherein a second resistance level is programmed by passage of a write current in an opposing second direction. The switching element is programmed to a selected resistance level to facilitate access to the selected resistance state of the memory element.


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