The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7973612 B1

PDF
Full Text
Expired
Date of Patent:
Jul. 05, 2011

Filed:

Apr. 26, 2009
Applicants:

Ashwin Raghunathan, Santa Clara, CA (US);

Marzio Pedrali-noy, San Diego, CA (US);

Inventors:

Ashwin Raghunathan, Santa Clara, CA (US);

Marzio Pedrali-Noy, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/099 (2006.01);
U.S. Cl.
CPC ...
Abstract

A supply-regulated Phase-locked loop (PLL) is provided. The PLL comprises a supply-regulating loop, a voltage-controlled oscillator (VCO), and a programmable decoupling capacitor array for the VCO. The capacitance of the VCO decoupling capacitor array is adjustable to be equal to N times C, where N is the current value of a multiplication factor of a divide-by-N circuit and Cis a unit capacitance characterized for a processing technology chosen for fabricating the decoupling capacitor array. When the PLL switches from one frequency band to another, a higher-order pole introduced by the VCO decoupling capacitor tracks the PLL reference frequency, thus improving the PLL operational stability.


Find Patent Forward Citations

Raghunathan, Ashwin. (2011). Supply-regulated phase-locked loop (pll) and method of using (U.S. Patent No. 7973612). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7973612

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