Sample-and-hold (s/h) circuit

Abstract

A sample-and-hold circuit () is provided that that includes a sample-and-hold switch (), an integrator circuit () designed to generate an output voltage (V) signal, and a bias voltage (V) source (). The sample-and-hold switch () incldues a first switch (), a second switch (), and a third switch (). The first switch () has a first gate (), a first source () and a first drain (), the second switch () has a second gate (), a second source () electrically coupled to a bulk region (), and a second drain (), and the third switch () has a third gate (), a third drain (), and a third source () coupled to the first source (). The integrator circuit () includes an output operational amplifier () having an inverting input (V) () coupled to the second drain () and a non-inverting input (V). The bias voltage (V) source () applies a bias voltage (V) to the third drain and the non-inverting input (V) to drive a gate-to-source voltage (V) of the second switch () to an optimum negative value that reduces a sub-threshold leakage current (I) and a Gate Induced Drain Lowering (GIDL) leakage current in the second switch (), and to drive a drain-to-source voltage (V) of the second switch () is biased at a low value equal to an offset voltage (V) of the output operational amplifier () to minimize a drain-to-bulk current (I) in the second switch ().