The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 05, 2011
Filed:
Mar. 12, 2007
Umesh Sharma, Santa Clara, CA (US);
Harry Yue Gee, Sunnyvale, CA (US);
Phillip Gene Holland, Los Gatos, CA (US);
Umesh Sharma, Santa Clara, CA (US);
Harry Yue Gee, Sunnyvale, CA (US);
Phillip Gene Holland, Los Gatos, CA (US);
Semiconductor Components Industries LLC, Phoenix, AZ (US);
Abstract
The present invention relates to a method of making a robust wafer level chip scale package and, in particular, a method that prevents cracking of the passivation layer during solder flow and subsequent multiple thermal reflow steps. In one embodiment, a passivation layer that is formed using an insulating material applied in a highly compressive manner is used. In another aspect, another layer is applied over the passivation layer to assist with preventing cracking of the passivation layer.