The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 28, 2011
Filed:
Jan. 25, 2008
Bartholomew Blaner, Underhill Center, VT (US);
Mary D. Brown, Austin, TX (US);
William E. Burky, Austin, TX (US);
Todd A. Venton, Austin, TX (US);
Bartholomew Blaner, Underhill Center, VT (US);
Mary D. Brown, Austin, TX (US);
William E. Burky, Austin, TX (US);
Todd A. Venton, Austin, TX (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method for implementing speculative clock gating of digital logic circuits in a multiple stage pipeline design includes generating, in a first pipeline stage n, a valid control signal that is input to a first register in a second pipeline stage n+1, the valid control signal indicative of when an operation is qualified to be performed by the second pipeline stage n+1; and generating, in the first pipeline stage, a speculative valid control signal that is used to gate a clock signal to a plurality of additional registers in the second pipeline stage, wherein the speculative valid control signal is generated using only a subset of a total number of control inputs used in generating the valid control signal, and wherein the clock signal is sent directly, without gating, to the first register in the second pipeline stage.