Test circuits of semiconductor memory device for multi-chip testing and method for testing multi chips

Abstract

A test circuit of a semiconductor memory device for performing a test in cooperation with a tester having a plurality of input/output pins connected to a plurality of input/output lines. The test circuit may include a first comparing unit adapted to compare, on a bit-by-bit basis, read data that may be read from memory cells corresponding to an address with expected data, and to output the comparison results as first comparison signals, a second comparing unit adapted to perform a logic operation on the first comparison signals and to generate a flag signal when determining a failure of at least one of the memory cells on the basis of the operation result, and a storage unit adapted to store the first comparison signals in response to the flag signal.