The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 28, 2011
Filed:
Jun. 29, 2009
Jae Min Jang, Gyeonggi-do, KR;
Yong Ju Kim, Gyeonggi-do, KR;
Sung Woo Han, Gyeonggi-do, KR;
Hee Woong Song, Gyeonggi-do, KR;
Ic Su OH, Gyeonggi-do, KR;
Hyung Soo Kim, Gyeonggi-do, KR;
Tae Jin Hwang, Gyeonggi-do, KR;
Hae Rang Choi, Gyeonggi-do, KR;
Ji Wang Lee, Gyeonggi-do, KR;
Chang Kun Park, Gyeonggi-do, KR;
Jae Min Jang, Gyeonggi-do, KR;
Yong Ju Kim, Gyeonggi-do, KR;
Sung Woo Han, Gyeonggi-do, KR;
Hee Woong Song, Gyeonggi-do, KR;
Ic Su Oh, Gyeonggi-do, KR;
Hyung Soo Kim, Gyeonggi-do, KR;
Tae Jin Hwang, Gyeonggi-do, KR;
Hae Rang Choi, Gyeonggi-do, KR;
Ji Wang Lee, Gyeonggi-do, KR;
Chang Kun Park, Gyeonggi-do, KR;
Hynix Semiconductor Inc., Gyeonggi-do, KR;
Abstract
A delay locked loop (DLL) circuit includes a phase detection unit configured to generate a phase detection signal by comparing a phase of a reference clock signal with a phase of a feedback clock signal. An update control apparatus is configured to generate a valid interval signal and an update control signal by determining a difference between the number of first logical values and the number of second logical values of the phase detection signal in response to the reference clock signal. A shift register configured to update a delay value granted to a delay line in response to the update control signal when the valid interval signal is enabled.