The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 21, 2011

Filed:

May. 16, 2008
Applicant:

Lukas Daellenbach, Altdorf, DE;

Inventor:

Lukas Daellenbach, Altdorf, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

The invention relates to a method and a system for routing electric circuits in integrated circuit chip design. Specifically, the invention encompasses the steps of performing a congestion analysis for a given routed placement of cells containing said electric circuits on a chip; defining a critical area on said chip based on congestion information; analyzing actual wiring quality within said critical area; comparing an actual wiring quality of said critical area with a reference wiring quality of said critical area; and rerouting said critical area based on a comparison between the actual wiring quality and the reference wiring quality.


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