The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 21, 2011
Filed:
Jan. 14, 2008
Marta Zorrilla, Fontenay le Fleury, FR;
Vivian Blanchard, Saint Germain En Laye, FR;
Marta Zorrilla, Fontenay le Fleury, FR;
Vivian Blanchard, Saint Germain En Laye, FR;
Bull S.A., Les Clayes Sous Bois, FR;
Abstract
The invention relates to an automated method for inserting dummy surfaces () into the various layers of the physical design () of multilayer integrated circuits organized in interconnected units () containing interconnected blocks () composed of interconnected cells (), implemented by an integrated circuit design system (). The multilayer integrated circuit design (), stored in the design system () is implemented layer by layer, through selective insertion of patterns of dummy surfaces (), the selective insertion is based on an insertion hierarchy that respects the hierarchy of the physical design () of the integrated circuits, by means of individual implementation of the interconnected blocks () and first interconnection routing () for said interconnected blocks () and individual implementation of the interconnected units () and second interconnection routing () for said interconnected units (). The patterns of dummy surfaces are established selectively in accordance with the design of the blocks () of the integrated circuit.