The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 21, 2011

Filed:

Dec. 13, 2004
Applicants:

Brad W. Simeral, San Francisco, CA (US);

Roman Surgutchik, Santa Clara, CA (US);

Joshua Titus, Sunnyvale, CA (US);

Anand Srinivasan, San Jose, CA (US);

Edward M. Veeser, Austin, TX (US);

James P. Reilley, Sunnyvale, CA (US);

Inventors:

Brad W. Simeral, San Francisco, CA (US);

Roman Surgutchik, Santa Clara, CA (US);

Joshua Titus, Sunnyvale, CA (US);

Anand Srinivasan, San Jose, CA (US);

Edward M. Veeser, Austin, TX (US);

James P. Reilley, Sunnyvale, CA (US);

Assignee:

Nvidia Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/00 (2006.01); G06F 1/12 (2006.01); G06F 13/42 (2006.01);
U.S. Cl.
CPC ...
Abstract

A speculative transfer mechanism transfers a source synchronous read request from a first clock domain to a second clock domain. The address portion having address information is transferred to the second clock domain in response to detecting a source synchronous address strobe latching signal. A pointer is generated in response to detecting the address strobe latching signal and passed into the second clock domain. In one embodiment, a pointer is retimed to be stable for a timing window for which a crossover of the address portion may be performed in the second clock domain. Request logic in the second clock domain generates a read command based on the address portion and the pointer.


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