The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 21, 2011

Filed:

Jan. 16, 2007
Applicant:

Tomoyuki Ishizu, Kyoto, JP;

Inventor:

Tomoyuki Ishizu, Kyoto, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/148 (2006.01); H01L 29/04 (2006.01);
U.S. Cl.
CPC ...
Abstract

An active region and an isolation region are formed in the surface of a silicon semiconductor substrate having a (100) crystal plane as a principal surface. A gate insulating film and a gate electrode are formed on the active region in this order. A stress control film is formed to cover part of the active region where the gate electrode is not formed, the isolation region, the top surface of the gate electrode and sidewalls. A pair of stress control regions are formed to sandwich the gate electrode in the gate width direction of the gate electrode. In the stress control regions, the stress control film is not formed, or alternatively, a stress control film thinner than the stress control film formed on the gate electrode is formed.


Find Patent Forward Citations

Ishizu, Tomoyuki. (2011). Semiconductor device and method for manufacturing the same for improving the performance of mis transistors (U.S. Patent No. 7964899). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7964899

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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