The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 14, 2011
Filed:
Dec. 04, 2007
Marc R. Faucher, South Burlington, VT (US);
Hillery C. Hunter, Somers, NY (US);
William R. Reohr, Ridgefield, CT (US);
Peter A. Sandon, Essex Junction, VT (US);
Vijayalakshmi Srinivasan, New York, NY (US);
Arnold S. Tran, South Burlington, VT (US);
Marc R. Faucher, South Burlington, VT (US);
Hillery C. Hunter, Somers, NY (US);
William R. Reohr, Ridgefield, CT (US);
Peter A. Sandon, Essex Junction, VT (US);
Vijayalakshmi Srinivasan, New York, NY (US);
Arnold S. Tran, South Burlington, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method of integrating a hybrid architecture in a set associative cache having a first type of memory structure for one or more ways in each congruence class, and a second type of memory structure for the remaining ways of the congruence class, includes determining whether a memory access request results in a cache hit or a cache miss; in the event of a cache miss, determining whether LRU way of the first type memory structure is also the LRU way of the entire congruence class, and if not, then copying the contents of the LRU way of the first type memory structure into the LRU way of the entire congruence class, and filling the LRU way of the first type memory structure with a new cache line in the event of a cache miss; and updating LRU bits, depending upon the results of the memory access request.