The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 14, 2011
Filed:
Nov. 15, 2006
Tobias Gemmeke, Boeblingen, DE;
Jens Leenstra, Bosdorf, DE;
Nicolas Maeding, Holzgertingen, DE;
Kerstin Schelm, Stuttgart, DE;
Tobias Gemmeke, Boeblingen, DE;
Jens Leenstra, Bosdorf, DE;
Nicolas Maeding, Holzgertingen, DE;
Kerstin Schelm, Stuttgart, DE;
International Business Machines Corporation, Armonk, NY (US);
Abstract
An electronic computing circuit for implementing a method for reducing the bit width of two operands from a bit length N to a reduced bit length M, thus, M<N. To enable a wider re-usage of existing designs or building blocks being all specialized to the usual bit length of a power of 2 (8, 16, 32, 64 etc.), the chip structure of which is already highly optimized in regard of speed and space savings, a circuit is implemented as an addend width reduction circuit to perform the steps of: receiving said two N-bit operands as an input, adding the (N−M+1) most significant bits of said two N-bit operands separately in an auxiliary adder logic, calculating at least the two most significant bits of reduced-bit-length output operands in a decision logic processing the add result of said auxiliary adder logic, such that a predetermined post-processing can be correctly performed with said output operands.