The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 14, 2011
Filed:
May. 09, 2006
Masashi Ogawa, Minato-ku, JP;
Hiroshi Wabuka, Minato-ku, JP;
Masashi Ogawa, Minato-ku, JP;
Hiroshi Wabuka, Minato-ku, JP;
NEC Corporation, Tokyo, JP;
Abstract
A method of creating a power pin model of an LSI having appropriate analysis accuracy in consideration of information on positions within the LSI is provided. A divided cell size decision unit automatically decides a divided cell size of the LSI from power supply circuit network wire information, transistor structure information, analysis frequency information, size information, and element arrangement information of the LSI as well as from a semiconductor integrated circuit entire power pin model. A model creation unit allocates a model of an active section and a model of an internal capacitance section, including the positional information, within the LSI to the cells at an appropriate proportion, and a model coupling unit couples the models in each cell to create a power pin model of the LSI. Here, the size of each divided cell is determined to be electrically sufficiently smaller than a wavelength corresponding to an upper limit analysis frequency derived from power supply circuit network wire information, transistor structure information, and analysis frequency information.