The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 14, 2011
Filed:
Jun. 08, 2006
Qamar A. Shams, Yorktown, VA (US);
Michael J. Logan, Chesapeake, VA (US);
Robert L. Fox, Hayes, VA (US);
Christopher L. Fox, Legal Representative, Yorktown, VA (US);
Melanie L. Fox, Legal Representative, Hayes, VA (US);
John C. Ingham, Alexandria, VA (US);
Sean A. Laughter, Chester, VA (US);
Theodore R. Kuhn, Iii, Fredericksburg, VA (US);
James K. Adams, Gloucester, VA (US);
Walter C. Babel, Iii, Smithfield, VA (US);
Qamar A. Shams, Yorktown, VA (US);
Michael J. Logan, Chesapeake, VA (US);
Robert L. Fox, Hayes, VA (US);
Christopher L. Fox, legal representative, Yorktown, VA (US);
Melanie L. Fox, legal representative, Hayes, VA (US);
John C. Ingham, Alexandria, VA (US);
Sean A. Laughter, Chester, VA (US);
Theodore R. Kuhn, III, Fredericksburg, VA (US);
James K. Adams, Gloucester, VA (US);
Walter C. Babel, III, Smithfield, VA (US);
Abstract
A self-contained avionics sensing and flight control system is provided for an unmanned aerial vehicle (UAV). The system includes sensors for sensing flight control parameters and surveillance parameters, and a Global Positioning System (GPS) receiver. Flight control parameters and location signals are processed to generate flight control signals. A Field Programmable Gate Array (FPGA) is configured to provide a look-up table storing sets of values with each set being associated with a servo mechanism mounted on the UAV and with each value in each set indicating a unique duty cycle for the servo mechanism associated therewith. Each value in each set is further indexed to a bit position indicative of a unique percentage of a maximum duty cycle for the servo mechanism associated therewith. The FPGA is further configured to provide a plurality of pulse width modulation (PWM) generators coupled to the look-up table. Each PWM generator is associated with and adapted to be coupled to one of the servo mechanisms.