Programmable and pausable clock generation unit

Abstract

In an example embodiment, a clock generation circuit comprises two programmable ring oscillators arranged and configured to operate in a mutually exclusive manner, and a variable programmable delay element (not shown). An input programming pattern is provided as an input to the oscillating circuit, the programming pattern providing data representative of the sequence of frequencies at which the clock signal is required to be generated. The outputs of both the oscillators are connected to a clock switch (), from which the generated clock signal is output. When a request for a change of frequency is received, the currently idle oscillator is first activated with the next required frequency, the output of the currently operative oscillator is then gated when the clock signal thereof goes low. Next, the previously gated output of oscillator is un-gated when its output goes low, and then oscillator is de-activated.