The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 14, 2011
Filed:
Oct. 27, 2008
Hugh T. Mair, Fairview, TX (US);
Robert L. Pitts, Dallas, TX (US);
Alice Wang, Allen, TX (US);
Sumanth K. Gururjarao, Dallas, TX (US);
Ramaprasath Vilangudipitchai, Plano, TX (US);
Gordon Gammie, Plano, TX (US);
Uming Ko, Plano, TX (US);
Hugh T. Mair, Fairview, TX (US);
Robert L. Pitts, Dallas, TX (US);
Alice Wang, Allen, TX (US);
Sumanth K. Gururjarao, Dallas, TX (US);
Ramaprasath Vilangudipitchai, Plano, TX (US);
Gordon Gammie, Plano, TX (US);
Uming Ko, Plano, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
Memory power management systems and methods are provided. One embodiment of the present invention includes a memory power management system. The system comprises a first low dropout (LDO) regulator that provides an active operating voltage that is derived from a first supply voltage to power a memory array during an active mode. The system further comprises a second LDO regulator that provides a minimum memory retention voltage that is derived from a second supply voltage to power the memory array in a standby mode, wherein the second supply voltage also powers at least one peripheral circuit for reading from and/or writing to the memory array.