The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 14, 2011

Filed:

Oct. 26, 2010
Applicants:

Stephen Bradley Ippolito, Croton on Hudson, NY (US);

Darrell L. Miles, Wappingers Falls, NY (US);

Peilin Song, Lagrangeville, NY (US);

John D. Sylvestri, Poughkeepsie, NY (US);

Inventors:

Stephen Bradley Ippolito, Croton on Hudson, NY (US);

Darrell L. Miles, Wappingers Falls, NY (US);

Peilin Song, Lagrangeville, NY (US);

John D. Sylvestri, Poughkeepsie, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G01N 21/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A structure for locating a fault in a semiconductor chip. The chip includes a substrate on a dielectric interconnect. A first electrical response image of the chip, which includes a spot representing the fault, is overlayed on a first reflection image for monochromatic light in an optical path from an optical microscope through a SIL/NAIL and into the chip. The index of refraction of the substrate exceeds that of the dielectric interconnect and is equal to that of the SIL/NAIL. A second electrical response image of the chip is overlayed on a second reflection image for the monochromatic light in an optical path in which an optical stop prevents all subcritical angular components of the monochromatic light from being incident on the SIL/NAIL. If the second electrical response image includes or does not include the spot, then the fault is in the substrate or the dielectric interconnect, respectively.


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