The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 14, 2011
Filed:
Feb. 29, 2008
Hans Martin Von Staudt, Kingston Bagpuze, GB;
Alan Somerville, New Castle Upon Tyne, GB;
Hans Martin Von Staudt, Kingston Bagpuze, GB;
Alan Somerville, New Castle Upon Tyne, GB;
Dialog Semiconductor GmbH, Kirchheim/Teck-Nabern, DE;
Abstract
A CMOS driver test configuration, which allows both leakage current and load current testing, using a single monitor, or current meter, located in a power lead of a tester connected to a power pad servicing the driver circuits. Both leakage testing and load current testing for CMOS drivers is described. The test configuration allows a plurality of driver circuits connected in parallel between power pads to be tested simultaneously. An ESD device, internal to the chip, is used as a load during load current testing in chip testing, and an external load is used during package testing in order to include the bonding means between the chip output pad of the driver and the package I/O pin in the current path during load current testing.