The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 14, 2011

Filed:

Jan. 24, 2006
Applicants:

Salvatore Leonardi, Aci Sant'Antonio, IT;

Roberto Modica, Catania, IT;

Inventors:

Salvatore Leonardi, Aci Sant'Antonio, IT;

Roberto Modica, Catania, IT;

Assignee:

STMicroelectronics, S.r.l., Agrate Brianza, IT;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/76 (2006.01);
U.S. Cl.
CPC ...
Abstract

A process for manufacturing an electronic semiconductor device, wherein a SOI wafer is provided, formed by a bottom layer of semiconductor material, an insulating layer, and a top layer of semiconductor material, stacked on top of one another; alignment marks are formed in the top layer; an implanted buried region is formed, aligned to the alignment marks; a hard mask is formed on top of the top layer so as to align it to the alignment marks; using the hard mask, the top layer is selectively removed so as to form a trench extending up to the insulating layer; there a lateral-insulation region in the trench, that is contiguous to the insulating layer and delimits with the latter an insulated well of semiconductor material; and electronic components are formed in the top layer.


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