The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 07, 2011
Filed:
Dec. 04, 2007
Tapan J. Chakraborty, Princeton Junction, NJ (US);
Chen-huan Chiang, Princeton Junction, NJ (US);
Suresh Goyal, Warren, NJ (US);
Michele Portolan, Blandshardstown, IE;
Bradford Gene Van Treuren, Lambertville, NJ (US);
Tapan J. Chakraborty, Princeton Junction, NJ (US);
Chen-Huan Chiang, Princeton Junction, NJ (US);
Suresh Goyal, Warren, NJ (US);
Michele Portolan, Blandshardstown, IE;
Bradford Gene Van Treuren, Lambertville, NJ (US);
Alcatel-Lucent USA Inc., Murray Hill, NJ (US);
Abstract
The present invention provides a new hardware description language for chip-level JTAG testing. This new hardware description language, referred to as New BSDL (NSDL), enables testing resources of a system-on-chip to be described, thereby enabling the system-on-chip to be described in a manner that facilitates testing of the system-on-chip. The present invention provides a bottom-up approach to describing a system-on-chip. The present invention supports algorithmic descriptions of each of the components of the system-on-chip, and supports an algorithmic description of interconnections between the components of the system-on-chip, thereby enabling generation of an algorithmic description of the entire system-on-chip or portions of the system-on-chip.