The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 07, 2011
Filed:
Jun. 26, 2008
George J Chen, Union City, CA (US);
Gilda Garreton, Mountain View, CA (US);
Steven M Rubin, Portola Valley, CA (US);
Robert E Mains, Morgan Hill, CA (US);
George J Chen, Union City, CA (US);
Gilda Garreton, Mountain View, CA (US);
Steven M Rubin, Portola Valley, CA (US);
Robert E Mains, Morgan Hill, CA (US);
Oracle America, Inc., Redwood City, CA (US);
Abstract
Various methods and apparatus for executing a multithreaded algorithm that performs a static timing analysis of an integrated circuit chip (chip) include logic for traversing the chip to identify a plurality of components (cells or nodes) within a chip circuit of the chip. A waveform graph is defined for the identified nodes. One or more virtual graphs are generated from the waveform graph. The plurality of nodes in the one or more virtual graphs are processed using multiple threads to obtain quadruplet of time domain dataset values representing the different modes of propagation for each node. A timing check is performed at an end node of the virtual graphs using the quadruplet of time domain dataset values to determine any timing violation within the chip design.