The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7956661 B1

PDF
Full Text
Expired
Date of Patent:
Jun. 07, 2011

Filed:

Jan. 29, 2009
Applicant:

Hirohisa Machida, Tokyo, JP;

Inventor:

Hirohisa Machida, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 3/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present invention provides a standard cell and a scan flip flop circuit capable of introducing a scan test also to a system LSI having an ACS circuit. One standard cell is configured by: a 3-input selection circuit for selecting one signal from three input signals; and a flip flop circuit. The 3-input selection circuit receives a control signal and a test signal at its control input part and its first input part, respectively. First and second signals are supplied to second and third input parts, and a selection signal is supplied to a selector input part. On the basis of the control signal and the selection signal, any of the signals input to the first to third input parts is output from the output part.


Find Patent Forward Citations

Machida, Hirohisa. (2011). Standard cell and semiconductor device (U.S. Patent No. 7956661). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7956661

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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