The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 07, 2011

Filed:

May. 26, 2009
Applicants:

Takao Arai, Kanagawa, JP;

Sachiko Shirai, Legal Representative, Kanagawa, JP;

Inventors:

Takao Arai, Kanagawa, JP;

Sachiko Shirai, legal representative, Kanagawa, JP;

Assignee:

Renesas Electronics Corporation, Kawasaki-shi, Kanagawa, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/8248 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of a semiconductor device, which includes an insulated-gate FET and an electronic element, includes three steps. The first step is the step of forming a trench gate of the insulated-gate FET in a first region of a semiconductor base and a trench element-isolation layer in a second region of the semiconductor base, simultaneously. The second step is the step of forming a first diffusion layer of the insulated-gate FET on a side of the trench gate and a second diffusion layer of the electronic element in a region surrounded by the trench element-isolation layer, simultaneously. The third step is the step of forming a third diffusion layer of the insulated-gate FET in the first diffusion layer and a fourth diffusion layer of the electronic element in the second diffusion layer, simultaneously.


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