The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 07, 2011
Filed:
Feb. 13, 2007
Hye-young Ryu, Seoul, KR;
Young-hoon Yoo, Suwon-si, KR;
Jang-soo Kim, Suwon-si, KR;
Sung-man Kim, Seoul, KR;
Kyung-wook Kim, Seoul, KR;
Hyang-shik Kong, Suwon-si, KR;
Young-goo Song, Suwon-si, KR;
Hye-Young Ryu, Seoul, KR;
Young-Hoon Yoo, Suwon-si, KR;
Jang-Soo Kim, Suwon-si, KR;
Sung-Man Kim, Seoul, KR;
Kyung-Wook Kim, Seoul, KR;
Hyang-Shik Kong, Suwon-si, KR;
Young-Goo Song, Suwon-si, KR;
Samsung Electronics Co., Ltd., Suwon-Si, KR;
Abstract
A thin film transistor array panel is provided, which includes: a gate line, a gate insulating layer, and a semiconductor layer sequentially formed on a substrate; a data line and a drain electrode formed at least on the semiconductor layer; a first passivation layer formed on the data line and the drain electrode and having a first contact hole exposing the drain electrode at least in part; a second passivation layer formed on the first passivation layer and having a second contact hole that is disposed on the first contact hole and has a first bottom edge placed outside the first contact hole and a second bottom edge placed inside the first contact hole; and a pixel electrode formed on the second passivation layer and connected to the drain electrode through the first and the second contact holes.