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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7954114 B1

PDFFull Text
Date of Patent:
May. 31, 2011

Filed:

Jan. 26, 2006

Firmware socket module for fpga-based pipeline processing

Applicants:

Roger D. Chamberlain, Saint Louis, MO (US);

E. F. Berkley Shands, Kirkwood, MO (US);

Benjamin C. Brodie, University City, MO (US);

Michael Henrichs, Saint Louis, MO (US);

Jason R. White, Manchester, MO (US);

Inventors:

Roger D. Chamberlain, Saint Louis, MO (US);

E. F. Berkley Shands, Kirkwood, MO (US);

Benjamin C. Brodie, University City, MO (US);

Michael Henrichs, Saint Louis, MO (US);

Jason R. White, Manchester, MO (US);

Assignees:

Exegy Incorporated, St. Louis, MO (US);

Washington University, St. Louis, MO (US);

Attorney:

Thompson Coburn LLP

Primary Examiner:

Andy Ho

Assistant Examiner:

Shih-Wei Kraft

Int. Cl.
CPC ...
G06F 9/44 (2006.01); G06F 9/45 (2006.01); G06F 13/00 (2006.01); G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A firmware socket module is deployed on a reconfigurable logic device, wherein the firmware socket module is configured to provide both commands and target data to an entry point in a data processing pipeline, wherein each command defines a data processing operation that is to be performed by the data processing pipeline, and wherein the target data corresponds to the data upon which the data processing pipeline performs its commanded data processing operation. Also, the firmware socket module may be configured to (1) access an external input descriptor pool buffer that defines an order in which commands and target data are to be provided to the data processing pipeline, and (2) transfer the commands and target data from an external memory to the data processing pipeline in accordance with the defined order.

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Quick Actions:

Chamberlain, Roger. (2011). Firmware socket module for fpga-based pipeline processing (U.S. Patent No. 7954114). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7954114

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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