The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 31, 2011
Filed:
Jan. 14, 2008
David H. Allen, Rochester, MN (US);
Roger J. Gravrok, Eau Claire, WI (US);
Kenneth A. Van Goor, Fall Creek, WI (US);
David H. Allen, Rochester, MN (US);
Roger J. Gravrok, Eau Claire, WI (US);
Kenneth A. Van Goor, Fall Creek, WI (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
An integrated circuit includes a first clock island, a second clock island, a clock generator, and a first programmable delay element. The first clock island is configured to receive a first clock signal. The second clock island is configured to receive a second clock signal. The clock generator is configured to provide a generated clock signal and the first and second clock signals are based on the generated clock signal. The first programmable delay element is coupled between the clock generator and the first clock island. The first programmable delay element is configured to receive the generated clock signal and provide the first clock signal. The integrated circuit is configured to account for a clock skew between the first and second clock signals when information is transferred between the first and second clock islands. In this manner, a predetermined amount of the clock skew may be introduced between the first and second clock signals to smear out, over time, instantaneous power supply current demands of respective logic within the first and second clock islands.