The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 31, 2011

Filed:

Jun. 12, 2007
Applicants:

John Zijun Shen, Winchester, MA (US);

Paul D. Krivacek, North Andover, MA (US);

Thomas J. Barber, Jr., Bolton, MA (US);

Lidwine Martinot, Cottenham, GB;

Aiguo Yan, North Andover, MA (US);

Marko Kocic, Somerville, MA (US);

Inventors:

John Zijun Shen, Winchester, MA (US);

Paul D. Krivacek, North Andover, MA (US);

Thomas J. Barber, Jr., Bolton, MA (US);

Lidwine Martinot, Cottenham, GB;

Aiguo Yan, North Andover, MA (US);

Marko Kocic, Somerville, MA (US);

Assignee:

MediaTek Inc., Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 15/76 (2006.01); G06F 9/302 (2006.01);
U.S. Cl.
CPC ...
Abstract

A joint detection system is configured to perform joint detection of received signals and includes a joint detection accelerator and a host processor. The joint detection accelerator may include a memory unit to store input data values, intermediate results and output data values; one or more computation units to process the input data values and the intermediate results, and to provide output data values to the memory unit; a controller to control the memory and the one or more computation units to perform joint detection processing; and an external interface to receive the input data values from the host processor and to provide output data values to the host processor. The computation units may include a complex multiply accumulate unit, a simplified complex multiply accumulate unit and a normalized floating point divider. The memory unit may include an input memory, a matrix memory, a main memory and an output memory.


Find Patent Forward Citations

Loading…