The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 31, 2011
Filed:
Feb. 21, 2008
I-kang Yu, Palo Alto, CA (US);
David Q. Chow, San Jose, CA (US);
Charles C. Lee, Cupertino, CA (US);
Abraham Chih-kang MA, Fremont, CA (US);
Ming-shiang Shen, Taipei Hsien, TW;
I-Kang Yu, Palo Alto, CA (US);
David Q. Chow, San Jose, CA (US);
Charles C. Lee, Cupertino, CA (US);
Abraham Chih-Kang Ma, Fremont, CA (US);
Ming-Shiang Shen, Taipei Hsien, TW;
Super Talent Electronics, Inc., San Jose, CA (US);
Abstract
High endurance non-volatile memory devices (NVMD) are described. A high endurance NVMD includes an I/O interface, a NVM controller, a CPU along with a volatile memory subsystem and at least one non-volatile memory (NVM) module. The volatile memory cache subsystem is configured as a data cache subsystem. The at least one NVM module is configured as a data storage when the NVMD is adapted to a host computer system. The I/O interface is configured to receive incoming data from the host to the data cache subsystem and to send request data from the data cache subsystem to the host. The at least one NVM module may comprise at least first and second types of NVM. The first type comprises SLC flash memory while the second type MLC flash. The first type of NVM is configured as a buffer between the data cache subsystem and the second type of NVM.