The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 31, 2011
Filed:
Nov. 16, 2005
Integrated circuit package having inductance loop formed from same-pin-to-same-bonding-pad structure
Yido Koo, Seoul, KR;
Hyungki Huh, Seoul, KR;
Kang Yoon Lee, Seoul, KR;
Jeong-woo Lee, Seoul, KR;
Joonbae Park, Seoul, KR;
Kyeongho Lee, Seoul, KR;
Yido Koo, Seoul, KR;
Hyungki Huh, Seoul, KR;
Kang Yoon Lee, Seoul, KR;
Jeong-Woo Lee, Seoul, KR;
Joonbae Park, Seoul, KR;
Kyeongho Lee, Seoul, KR;
GCT Semiconductor, Inc., San Jose, CA (US);
Abstract
An integrated circuit package includes an inductance loop formed from a connection of bonding wires and one or more input/output (I/O) package pins. In one embodiment, the inductance loop is formed from a first wire which connects a bonding pad on the integrated circuit chip to an I/O pin of the package and a second wire which connects the same bonding pad to the same pin. By forming the inductor loop within the limits of the integrated circuit package, a substantial reduction in space requirements is realized, which, in turn, promotes miniaturization.