The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 31, 2011
Filed:
Sep. 11, 2008
Eiji Oue, Mobara, JP;
Takuo Kaitoh, Mobara, JP;
Hidekazu Miyake, Mobara, JP;
Toshio Miyazawa, Chiba, JP;
Yuichiro Takashina, Ichihara, JP;
Eiji Oue, Mobara, JP;
Takuo Kaitoh, Mobara, JP;
Hidekazu Miyake, Mobara, JP;
Toshio Miyazawa, Chiba, JP;
Yuichiro Takashina, Ichihara, JP;
Hitachi Displays, Ltd., Chiba, JP;
Abstract
In a display device of the present invention which forms thin film transistors on a substrate, the thin film transistor comprises: a silicon nitride film which is formed on the substrate in a state that the silicon nitride film covers a gate electrode; a silicon oxide film which is selectively formed on the silicon nitride film; a semiconductor layer which is formed at least on an upper surface of the silicon oxide film and includes a pseudo single crystal layer or a polycrystalline layer; and a drain electrode and a source electrode which are formed on an upper surface of the semiconductor layer by way of a contact layer, wherein either one of the pseudo single crystal layer and the poly-crystalline layer is formed by crystallizing the amorphous silicon layer, and a peripheral-side wall surface of the pseudo single crystal layer or the polycrystalline layer is contiguously constituted with a peripheral-side wall surface of the silicon oxide film below the pseudo single crystal layer or the polycrystalline layer without a stepped portion.