Scan chain circuitry for delay fault testing of logic circuits

Abstract

Scan chain circuitry is provided for performing scan chain testing of integrated circuits. The integrated circuits being tested may include programmable logic. The scan chain circuitry may include scan chain cells. Each scan chain cell may have a first logic circuit that receives a scan enable signal. When the scan enable signal is asserted, the scan chain cells may be connected to form a scan chain for test data loading and unloading. Each scan chain cell may also include a second logic circuit. The second logic circuit in each scan chain cell may receive a test enable signal. Signal transitions may be created at the output of scan chain cells by loading the scan chain cells with data, deasserting the scan enable signal while the test enable signal is asserted, and applying a clock. At speed delay fault tests may be performed using the scan chain circuitry.