The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 24, 2011

Filed:

Sep. 25, 2007
Applicants:

Mathew R. Henry, Fogelsville, PA (US);

Douglas D. Lopata, Boyertown, PA (US);

Richard J. Mcpartland, Nazareth, PA (US);

Hai Quang Pham, Hatfield, PA (US);

Wayne E. Werner, Coopersburg, PA (US);

Inventors:

Mathew R. Henry, Fogelsville, PA (US);

Douglas D. Lopata, Boyertown, PA (US);

Richard J. McPartland, Nazareth, PA (US);

Hai Quang Pham, Hatfield, PA (US);

Wayne E. Werner, Coopersburg, PA (US);

Assignee:

Agere Systems Inc., Allentown, PA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/22 (2006.01); G11C 8/18 (2006.01); G11C 7/04 (2006.01); G11C 7/02 (2006.01);
U.S. Cl.
CPC ...
Abstract

Certain embodiments of the inventions provide an integrated circuit (IC) having a processor operatively coupled to a PVT (process-voltage-temperature) source and an adjustable memory. The processor receives from the source an input characterizing the present PVT condition and generates a command for the memory based on that input. In response to the command, the memory adjusts its internal circuit structure, clock speed, and/or operating voltage(s) to optimize its performance for the present PVT condition. Advantageously, the ability to adjust the memory so that it can maintain its functionality and deliver an acceptable level of performance under unfavorable PVT conditions provides additional flexibility in choosing circuit design options, which can produce area savings and/or increase the yield of acceptable ICs during manufacture.


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