The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 24, 2011

Filed:

Apr. 21, 2009
Applicant:

Shinya Kawakami, Kanagawa, JP;

Inventor:

Shinya Kawakami, Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 19/003 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor integrated circuit device includes a target circuit of a low power consumption mode having at least one flip-flop circuit to which a clock signal is supplied in a normal operation mode and in a low power consumption mode, and a logic circuit to which each output of the at least one flip-flop circuit is input, wherein each of the flip-flop circuits includes a selector that selects a normal data signal in the normal operation mode, selects an inverted output of the flip-flop circuit in the low power consumption mode, based on an operation-mode switching signal that designates switching between the normal operation mode and the low power consumption mode, and inputs the selected signal to a data input terminal of the flip-flop circuit.


Find Patent Forward Citations

Quick Actions:

Kawakami, Shinya. (2011). Semiconductor integrated circuit device and countermeasure method against nbti degradation (U.S. Patent No. 7948261). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7948261

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…