Testable integrated circuit, system in package and test instruction set

Abstract

An integrated circuit die includes first and second test data inputs, a test data output, and a test arrangement for testing the integrated circuit die. The test arrangement includes a multiplexer coupled to the first and second test data inputs, a further multiplexer coupled to the test data output, a plurality of shift registers including an instruction register, each of the shift registers being coupled between the multiplexer and the further multiplexer, and a controller for controlling the multiplexers in response to the instruction register. Such a test arrangement facilitates JTAG compliant testing of a system in package (SiP) by providing a direct connection between the SiP test data input pin and the second test data input of the IC die, and the SiP test data output pin and the test data output of the IC die, thus facilitating the bypassing of other test arrangements in the SiP.