The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 24, 2011

Filed:

Jun. 06, 2008
Applicants:

Paul S. Andry, Yorktown Heights, NY (US);

Evan G. Colgan, Chestnut Ridge, NY (US);

Lawrence S. Mok, Brewster, NY (US);

Chirag S. Patel, Peekskill, NY (US);

David E. Seeger, Congers, NY (US);

Inventors:

Paul S. Andry, Yorktown Heights, NY (US);

Evan G. Colgan, Chestnut Ridge, NY (US);

Lawrence S. Mok, Brewster, NY (US);

Chirag S. Patel, Peekskill, NY (US);

David E. Seeger, Congers, NY (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/473 (2006.01); H01L 23/52 (2006.01);
U.S. Cl.
CPC ...
Abstract

Apparatus and methods are provided for integrating microchannel cooling modules within high-density electronic modules (e.g., chip packages, system-on-a-package modules, etc.,) comprising multiple high-performance IC chips. Electronic modules are designed such that high-performance (high power) IC chips are disposed in close proximity to the integrated cooling module (or cooling plate) for effective heat extraction. Moreover, electronic modules which comprise large surface area silicon carriers with multiple chips face mounted thereon are designed such that integrated silicon cooling modules are rigidly bonded to the back surfaces of such chips to increase the structural integrity of the silicon carriers.


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