The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 24, 2011
Filed:
Oct. 02, 2009
Yoon-dong Park, Yongin-si, KR;
Won-joo Kim, Hwaseong-si, KR;
June-mo Koo, Seoul, KR;
Suk-pil Kim, Yongin-si, KR;
Jae-woong Hyun, Uijeongbu-si, KR;
Jung-hoon Lee, Seoul, KR;
Yoon-Dong Park, Yongin-si, KR;
Won-Joo Kim, Hwaseong-si, KR;
June-Mo Koo, Seoul, KR;
Suk-Pil Kim, Yongin-si, KR;
Jae-Woong Hyun, Uijeongbu-si, KR;
Jung-Hoon Lee, Seoul, KR;
Samsung Electronics Co., Ltd., Gyeonggi-do, KR;
Abstract
The non-volatile memory device may include a semiconductor substrate having a body and a pair of fins. A bridge insulating layer may non-electrically connect upper portions of the pair of fins to define a void between the pair of fins. Outer surfaces of the pair of fins are the surfaces of the pair of fins that do not face the void and inner surfaces of the pair of fins are the surfaces of the pair of fins that do face the void. The non-volatile memory device may further include at least one control gate electrode that may cover at least a portion of outer surfaces of the pair of fins, may extend over the bridge insulating layer, and may be isolated from the semiconductor substrate. At least one pair of gate insulating layers may be between the at least one control gate electrode and the pair of fins, and at least one pair of storage nodes may be between the at least one pair of gate insulating layers and the at least one control gate electrode.