The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 24, 2011

Filed:

Dec. 04, 2006
Applicants:

IN Bok Baek, Chungcheongbuk-do, KR;

Seong Jae Lee, Daejeon, KR;

Jong Heon Yang, Daejeon, KR;

Chang Geun Ahn, Daejeon, KR;

Han Young Yu, Daejeon, KR;

Ki Ju Im, Daejeon, KR;

Inventors:

In Bok Baek, Chungcheongbuk-do, KR;

Seong Jae Lee, Daejeon, KR;

Jong Heon Yang, Daejeon, KR;

Chang Geun Ahn, Daejeon, KR;

Han Young Yu, Daejeon, KR;

Ki Ju Im, Daejeon, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/22 (2006.01);
U.S. Cl.
CPC ...
Abstract

Provided is a method of manufacturing a semiconductor device in which properties of photoresist through a lithography process are changed to form a dummy structure, and the structure is applied to a process of forming a gate electrode. The method includes the steps of: forming a buffer layer on the top of a semiconductor substrate; applying an inorganic photoresist on the buffer layer, and forming a photoresist pattern using a lithography process; thermally treating the photoresist pattern using a predetermined gas; uniformly depositing an insulating layer on the thermally treated structure, and etching the deposited layer by the deposited thickness in order to expose the thermally treated photoresist pattern; depositing an insulating layer on the etched structure, and etching the deposited insulating layer to expose the thermally treated photoresist pattern; removing the exposed photoresist pattern using an etching process; forming a gate oxide layer in the portion in which the photoresist pattern is removed; and forming a gate electrode on the gate oxide layer. Accordingly, in forming a structure for manufacturing a nano-sized device, the properties of the layer formed by a lithography process are improved through thermal treatment, and thus the structure used to manufacture various devices can be easily formed.


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