The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 24, 2011
Filed:
Dec. 10, 2008
Mikael T. Bjoerk, Adliswil, CH;
Oliver Hayden, Herzogenaurach, DE;
Heike E. Riel, Baech, CH;
Walter Heinrich Riess, Thalwil, CH;
Heinz Schmid, Waedenswil, CH;
Mikael T. Bjoerk, Adliswil, CH;
Oliver Hayden, Herzogenaurach, DE;
Heike E. Riel, Baech, CH;
Walter Heinrich Riess, Thalwil, CH;
Heinz Schmid, Waedenswil, CH;
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method for the fabrication of a semiconductor structure that includes areas that have different crystalline orientation and semiconductor structure formed thereby. The disclosed method allows fabrication of a semiconductor structure that has areas of different semiconducting materials. The method employs templated crystal growth using a Vapor-Liquid-Solid (VLS) growth process. A silicon semiconductor substrate having a first crystal orientation direction is etched to have an array of holes into its surface. A separation layer is formed on the inner surface of the hole for appropriate applications. A growth catalyst is placed at the bottom of the hole and a VLS crystal growth process is initiated to form a nanowire. The resultant nanowire crystal has a second different crystal orientation which is templated by the geometry of the hole.