The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7947566 B1

PDF
Full Text
Expired
Date of Patent:
May. 24, 2011

Filed:

Jan. 31, 2008
Applicants:

Howard Hao Chen, Yorktown Heights, NY (US);

Louis Lu-chen Hsu, Fishkill, NY (US);

Jack Allan Mandelman, Flat Rock, NC (US);

Inventors:

Howard Hao Chen, Yorktown Heights, NY (US);

Louis Lu-Chen Hsu, Fishkill, NY (US);

Jack Allan Mandelman, Flat Rock, NC (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/76 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor processing method includes providing a substrate, forming a plurality of semiconductor layers in the substrate, each of the semiconductor layers being distinct and selected from different groups of semiconductor element types. The semiconductor layers include a first, second, and third semiconductor layers. The method further includes forming a plurality of lateral void gap isolation regions for isolating portions of each of the semiconductor layers from portions of the other semiconductor layers.


Find Patent Forward Citations

Chen, Howard. (2011). Method and apparatus for making coplanar isolated regions of different semiconductor materials on a substrate (U.S. Patent No. 7947566). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7947566

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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