The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 24, 2011
Filed:
May. 05, 2009
Jin Gu Kim, Suwon-si, KR;
Young DO Kweon, Seoul, KR;
Hyung Jin Jeon, Gunpo-si, KR;
Seung Wook Park, Seoul, KR;
Hee Kon Lee, Hwaseong-si, KR;
Seon Hee Moon, Seoul, KR;
Jin Gu Kim, Suwon-si, KR;
Young Do Kweon, Seoul, KR;
Hyung Jin Jeon, Gunpo-si, KR;
Seung Wook Park, Seoul, KR;
Hee Kon Lee, Hwaseong-si, KR;
Seon Hee Moon, Seoul, KR;
Samsung Electro-Mechanics Co., Ltd., Suwon, KR;
Abstract
The present invention relates to a method of manufacturing a wafer level package including the steps of: preparing a substrate wafer including a plurality of pads formed on a bottom surface, a plurality of chips positioned on a top surface, and dicing lines for dividing the chips; forming external connection units on the pads; coating resin on the dicing lines by positioning masks on the substrate wafer to expose only the dicing lines; removing the masks; encapsulating the chips positioned between the resin by coating the chips with encapsulant; removing the resin coated on the dicing lines; and cutting a wafer level package along the dicing lines exposed by removing the resin into units.