The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 17, 2011
Filed:
Jun. 12, 2008
Applicants:
Alok Anand, Bangalore, IN;
Sajish Sajayan, Bangalore, IN;
Inventors:
Alok Anand, Bangalore, IN;
Sajish Sajayan, Bangalore, IN;
Assignee:
Texas Instruments Incorporated, Dallas, TX (US);
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G06F 9/45 (2006.01); G01R 31/28 (2006.01);
U.S. Cl.
CPC ...
Abstract
This invention transforms a circuit design at an asynchronous clock boundary using a flow involving register grouping, logic modification and level shifter and isolation cell insertion. The level shifter and isolation cell inserted are tested for proper location. The transformed circuit design is suitable for power consumption control by independent control of separate voltage domains.
Quick Actions:
Anand, Alok. (2011). Methodology for hierarchy separation at asynchronous clock domain boundaries for multi-voltage optimization using design compiler (U.S. Patent No. 7945875). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7945875
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile