The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 17, 2011
Filed:
Oct. 23, 2006
Hendrikus Petrus Elisabeth Vranken, Weert, NL;
Hendrikus Petrus Elisabeth Vranken, Weert, NL;
NXP B.V., Eindhoven, NL;
Abstract
An integrated circuit (IC) arrangement () comprises an integrated circuit () having a digital circuit portion () with a plurality of digital outputs (), each of the outputs being arranged to provide a test result in a test mode of the integrated circuit (). The arrangement () further comprises space compaction logic () comprising a space compaction network () having a plurality of compaction domains (), each domain being arranged to compact a plurality of test results into a further test result, and a spreading network () coupled between the plurality of digital outputs () and the space compaction network (), the spreading network being arranged to duplicate each test result from the digital outputs () to a number of compaction domains (). This space compaction logic (), which may be located on the ICor external thereto such as on a test apparatus or on a test interface, reduces the risk of fault cancellation or fault aliasing compared to SCLs without spreading network.