The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 17, 2011
Filed:
Dec. 15, 2008
Mrinal Bose, Austin, TX (US);
Jayanta Bhadra, Austin, TX (US);
Kenneth G. Davis, Woodville, AL (US);
Yaniv Fais, Tzur Moshe, IL;
Sharon Goldschlager, Tel-Aviv, IL;
Amit Hermony, Givat ada, IL;
Hillel Miller, Austin, TX (US);
Prashant U. Naphade, Cedar Park, TX (US);
Pankaj Sharma, Austin, TX (US);
Robert S. Slater, Raanana, IL;
Mrinal Bose, Austin, TX (US);
Jayanta Bhadra, Austin, TX (US);
Kenneth G. Davis, Woodville, AL (US);
Yaniv Fais, Tzur Moshe, IL;
Sharon Goldschlager, Tel-Aviv, IL;
Amit Hermony, Givat ada, IL;
Hillel Miller, Austin, TX (US);
Prashant U. Naphade, Cedar Park, TX (US);
Pankaj Sharma, Austin, TX (US);
Robert S. Slater, Raanana, IL;
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
An approach is provided to manage test transactors that interface with components of a hardware design. A first set of transactors is launched with the first set of transactors sending stimuli to various components that correspond to the first set of transactors. A manager receives signals when transactors of the first set have completed at which point a second set of transactors is identified that are dependent upon the first set transactors that completed. The second set of transactors is launched by the manager. The manager further facilitates transmission of data used by the various transactors. Transactors generate and provide stimuli to various components included in a hardware design, such as a System-on-a-Chip (SoC). Results from the hardware design are passed to the transactors which, in turn, pass the results back to the manager. In this manner, results from one transactor may be made available as input to another transactor.