The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7944265 B1

PDF
Full Text
Expired
Date of Patent:
May. 17, 2011

Filed:

Mar. 12, 2008
Applicants:

Christopher Tin Sing Lam, Hsinchu Hsien, TW;

Fu Cheng Wang, Hsinchu Hsien, TW;

Shou Fang Chen, Hsinchu Hsien, TW;

Inventors:

Christopher Tin Sing Lam, Hsinchu Hsien, TW;

Fu Cheng Wang, Hsinchu Hsien, TW;

Shou Fang Chen, Hsinchu Hsien, TW;

Assignee:

MStar Semiconductor, Inc., Hsinchu Hsien, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/04 (2006.01); H03K 3/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A clock generator includes a delta sigma modulator, a counter and a first phase lock loop. The delta sigma modulator sequentially generates a plurality of variable parameters according to a predetermined value and a first input clock signal. The counter, which is connected to the delta sigma modulator, is used to generate an output clock signal in accordance with a counting value and a second input clock signal. The counting value is relevant to the variable parameters. The first phase lock loop, which is connected to the output of the counter, is used to generate an objective clock signal in accordance with the output clock signal.


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Lam, Christopher Tin Sing. (2011). Clock generator, method for generating clock signal and fractional phase lock loop thereof (U.S. Patent No. 7944265). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7944265

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