The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 17, 2011

Filed:

Mar. 13, 2008
Applicant:

Kou Sasaki, Kanagawa, JP;

Inventor:

Kou Sasaki, Kanagawa, JP;

Assignee:

Renesas Electronics Corporation, Kawasaki-shi, Kanagawa, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01);
U.S. Cl.
CPC ...
Abstract

A first memory chip () and a second memory chip () mounted in this order on one surface of a mounting board () each have a rectangular planar shape and include a plurality of electrode pads formed in a single line along one side of the rectangle. An electrode pad line of the second memory chip () is formed in parallel with an electrode pad line of the first memory chip (). A chip select pad is disposed on an end of the electrode pad line. Control pads, address pads, or data pads () of the first memory chip () are wire bonded to first stitches () formed in a single line along one side of the rectangle. A chip select pad () and a chip select pad () are wire bonded to second stitches () formed in a line along a side adjacent to a side of the chip select pad (). Accordingly, an increase in package area is suppressed when a plurality of memory chips are stacked.


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