The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 10, 2011
Filed:
Mar. 19, 2008
Minimizing clock uncertainty on clock distribution networks using a multi-level de-skewing technique
Charlie Chornglii Hwang, Hopewell Junction, NY (US);
Jose Correia Neves, Poughkeepsie, NY (US);
Phillip John Restle, Katonah, NY (US);
Charlie Chornglii Hwang, Hopewell Junction, NY (US);
Jose Correia Neves, Poughkeepsie, NY (US);
Phillip John Restle, Katonah, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
Disclosed is a method of minimizing clock uncertainty using a multi-level de-skewing technique. The method includes the steps of obtaining a chip wherein at least a portion of the chip has a regular array of buffers on multiple levels, the buffers being driven by first drivers and the first drivers being driven by second drivers; grouping the buffers in a first direction to create clusters with the same number of buffer inputs, wherein if there are not the same number of buffer inputs in each cluster, then adding dummy buffers to the cluster with a deficient number of buffer inputs; wiring outputs of the first drivers together in a second direction, wherein the first and second directions are orthogonal; and wiring outputs of the second together in the second direction.