The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 10, 2011

Filed:

Feb. 23, 2007
Applicants:

Steven J. Baumgartner, Zumbro Falls, MN (US);

Timothy C. Buchholtz, Rochester, MN (US);

Andrew D. Davies, Rochester, MN (US);

Thomas W. Liang, Rochester, MN (US);

Andrew B. Maki, Rochester, MN (US);

Thomas Pham, Rochester, MN (US);

Dana M. Woeste, Mantorville, MN (US);

Daniel G. Young, Rochester, MN (US);

Inventors:

Steven J. Baumgartner, Zumbro Falls, MN (US);

Timothy C. Buchholtz, Rochester, MN (US);

Andrew D. Davies, Rochester, MN (US);

Thomas W. Liang, Rochester, MN (US);

Andrew B. Maki, Rochester, MN (US);

Thomas Pham, Rochester, MN (US);

Dana M. Woeste, Mantorville, MN (US);

Daniel G. Young, Rochester, MN (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03D 3/24 (2006.01); H04L 7/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A phase locked loop generates an output corresponding to a source synchronous input and an input link clock signal. A phase locking feedback system receives the input and an input link clock signal and detects phase deviations between the output and the input. The phase locking feedback system also adjusts an adjusted clock signal based on the phase deviations thereby causing the phase locking feedback system to generate the output so that the output has a steady phase relationship with the input. A first mechanism causes the phase locking feedback system not to track phase deviations between the output and the input upon occurrence of a first predefined event, thereby maintaining the adjusted clock signal at a current state.


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